Skip to main content
Ctrl
+
K
Welcome
Getting started
Weekly agenda
Content and learning objectives
Tools
Quartus and ModelSim
Git
Other resources
Github organization page
Discussion forum
Main content
1. FPGA technology
1.1. Programmable logic devices
1.2. Field Programmable Gate Arrays
2. VHDL
2.2. History
2.3. Design units and structure
2.4. Design flow
2.5. Objects and data types
2.6. Operators
2.7. Concurrent statements
2.8. Description styles
2.9. Testbenches
2.10. VHDL Process
2.11. Metastability and synchronization
2.12. Generic map
2.13. State machines
2.14. Packages and subprograms
3. Embedded systems
3.1. Nios II CPU
3.2. Soft core
3.3. Memory mapped interfaces
3.4. Hardware Abstraction Layer
3.5. Nios II system development
3.6. Interrupt handling
4. RTOS
4.1. uC/OS-II
4.2. Scheduling and task management
4.3. Latency & jitter
4.4. Intertask communication
4.4.1. Semaphores
4.4.2. Priority inversion
4.4.3. Messages
Exercises
Overview
VHDL
EX1: Your first FPGA project
EX2: Adder
EX3: 4-bit up-counter
EX4: State machine
Embedded systems
EX5: A basic Nios II system
EX6: Accessing Nios II memory mapped modules
EX7: Nios II interrupt handling
RTOS
EX8: A basic RTOS application
EX9: Semaphore example
Project
Project overview
P1: UART controller
P2: Microcontroller system
P3: RTOS
.md
.pdf
VHDL
VHDL
#
