2.2. History#
Before we explain the basic structure of a VHDL file and introduce some of the basic elements of the VHDL language, it may be interesting to understand the birth of VHDL.
Its development was motivated by a lack of adequate documentation for the behaviour and functionality of Application Specific Integrated Circuits (ASICs). In 1983 the US Department of Defence (DoD) initiated the process to develop a standardize documentation language for ASICs. Together with Intermetrics, IBM, and Texas Instrument, the first version of VHDL was finalized in 1985. VHDL was implemented in a format similar to a programming language and was in its first version a specification and modelling language that could be seen as an alternative to complex manuals.
As a natural development, this tool was soon extended to include simulation capabilities, and logic simulators where developed in the late 1980s. Finally, the logical next step was to implement the possibility to read VHDL and output a description of the physical implementation of the circuit. This process is referred to as logic synthesis.
VHDL is today a formal notation intended for use in all phases of the creation of electronic systems. It is both machine readable and human readable, and supports different needs in the design process:
Development: It can be used to describe the structure of a system, that is, how it is decomposed into subsystems and how these subsystems are interconnected; and it can be used to describe the function of these subsystems using familiar programming syntax.
Verification: It can be used to simulate the system. This allows the designer to test the correctness of the system before it is implemented in hardware.
Synthesis: It allows the detailed structure and function of a system to be converted into a physical implementation of the circuit.
2.2.1. IEEE standard#
To gain wide spread use, the maintenance of VHDL was handed over to Institute of Electrical and Electronic Engineers (IEEE). VHDL became an industry standard for specifying, verifying, and designing digital electronics. The first IEEE standard was released in 1987: IEEE 1076-1987. The number 1076 identifies VHDL. Verilog, which is the other common hardware description language, also has its own IEEE standard and is identified by the number 1364.
VHDL is in active development and the latest revision is currently: 1076-2019. However, the 2019 version has just been released and there is always a lag before the various development and simulation tools supports an updated standard. E.g., the VHDL standard 1076-1993 is still the default setting in Quartus Prime Lite, while for Modelsim it is 1076-2002. On both tools this can be changed, but for the moment only to 1076-2008:
Quartus: (Assignments –> Settings –> Compiler Settings –> VHDL input).
Modelsim: Right click on the file to be compiled (Properties –> VHDL), or through compile options in the menu bar for project wide setting (Compile –> Compile options)
The VHDL version are typically referred to as VHDL-year, e.g., VHDL-87, VHDL-93, VHDL-2008.
When writing VHDL descriptions, the IEEE standard can be invoked by adding the following statements to the top of your VHDL file.
library IEEE;
IEEE.std_logic_1164.all;
The IEEE library contains a number of packages, and the std_logic_1164 is the standard that describes the definitions of logic values and basic logic operations. It is needed in order for the development tool to interpret e.g. the basic syntax shown below that describes an OR operation.
Y <= A OR B;
Here we have two values A and B, and the result of the OR operation is assigned to Y. Without including the std_logic_1164, this operation would not be understood.
This is similar to how you e.g., need to include a header file in C/C++ or import a module in Python in order to reuse code defined in other files.
Supplementary suggested reading:
Chapter 5, section 5.1 in LaMeres [LaM19].